1. Field of the Invention
The present invention relates to electrically programmable nonvolatile memory cells such as electrically programmable read only memories (EPROM), electrically erasable programmable read only memories (EEPROM), and flash memories. This invention further relates to a method of fabricating such a nonvolatile memory.
2. Description of the Prior Art
A conventional nonvolatile memory cell will be explained below with reference to FIGS. 1A, 1B, and 1C.
FIG. 1A is a plan view of a conventional nonvolatile memory cell. Referring to FIG. 1A, first, an active region 4 including a source 1, drain 2, and channel region 3 are formed. Then, a floating gate 5 is formed between the source 1 and drain 2. Both edge portions of the floating gate 5 are superposed on a portion of the source 1 and drain 2. A control gate 6 is formed perpendicular to the active region 4 and on the floating gate 5. The source 1, drain 2, channel region 3, and floating gate 5 form a MOS transistor.
FIG. 1B is a cross-sectional view, taken along line A-A' of FIG. 1A. The source 1 and drain 2, which have a predetermined spacing, are formed in a predetermined portion of a P-type substrate 7. A portion of the substrate 7 between the source 1 and drain 2 becomes the channel region 3. A gate insulating layer 8 is formed on a portion of the substrate 7 between the source 1 and drain 2, and is superposed on an edge portion of each of the source 1 and drain 2. The floating gate 5 and control gate 6 are sequentially formed on the gate insulating layer 8.
FIG. 1C is a cross-sectional view, taken along line B-B' of FIG. 1A. Referring to FIG. 1C, two channel stop regions 10a and 10b are formed on a predetermined portion of the P-type substrate 7 in order to electrically isolate adjacent cells from each other in a nonvolatile memory cell array. The region of the P-type substrate 7 between the channel stop regions 10a and 10b defines the width of the active region 4. The insulating layer 8 is formed on a portion of the P-type substrate 7 between the channel stop regions 10a and 10b and is superposed on an edge portion of each of the channel stop regions 10a and 10b. The floating gate 5 and control gate 6 are sequentially formed on the gate insulating layer 8. Referring to FIGS. 1A to 1C, as described above, the floating gate 5 acts as a gate electrode of the field effect transistor and is formed under the control gate 6. The floating gate 5 is isolated from the source 1, drain 2, and channel region 3 of the transistor by the thin gate insulating layer 8. The control gate 6 is formed on the floating gate 5 and is isolated from the source 1, drain 2, and channel region 3 of the transistor, as well as from the floating gate 5 by an insulating layer 9. The control gate 6 forms a capacitor via the insulating layer 9 together with the floating gate 5. The threshold voltage (V.sub.T) is controlled depending on the amount of charge stored in the floating gate 5.
The operation of the conventional nonvolatile memory cell shown in FIGS. 1A, 1B, and 1C will be explained below. According to a program or erase operation of the cell, the threshold voltage V.sub.T of the transistor is programmed in one of two states, depending upon the amount of charge injected to the floating gate 5 from channel region 3 through thin gate insulating layer 8. The state of the programmed threshold voltage V.sub.T of the transistor is read by measuring the level of current flowing through the transistor under a condition where an appropriate voltage is applied to source 1, drain 2, and control gate 6.
More specifically, the level of current flowing in the transistor indicates whether the transistor of the cell selected by the control gate 6 is programmed in an "ON" or an "OFF" state. That is, in the read operation, the transistor logically reads "0" or "1", being electrically operated in an "ON" or an "OFF" state, respectively.
In a conventional EPROM, the programmed state is erased by irradiating ultraviolet while the erase operation is electrically performed by transferring charges stored in the floating gate 5 through a thin gate insulating layer 8 in an EEPROM or a flash memory.
FIG. 2 is an equivalent circuit diagram of a capacitor of the nonvolatile memory shown in FIGS. 1A, 1B, and 1C. Referring to FIG. 2, the floating gate 5 of the nonvolatile memory cell forms capacitors C1, C2, C3, and C4 with a source 1, drain 2, channel region 3, and control gate 6, respectively. In FIG. 2, the capacitance coupling for the floating gate 5 can be represented by a coupling ratio CC. The coupling ratio CC is obtained by the following formula (1). EQU CC=C1/(C1+C2+C3+C4) (1)
Therefore, when the nonvolatile memory cell is erased, the voltage across the floating gate 5 is determined by the voltage applied to the control gate 6. That is, the voltage value applied to the floating gate 5 depends on a value by which the voltage value across the control gate 6 is multiplied by the coupling ratio CC. As the coupling ratio CC is closer to 1.0, a nonvolatile memory cell operates more ideally in the program or erase operation.
However, the conventional nonvolatile memory cell shown in FIGS. 1A, 1B, and 1C has the following problems. In the conventional nonvolatile memory cell, in order to increase the coupling ratio, the capacitance value of capacitor C1 should be increased. In order to increase the capacitance of capacitor C1, the area of the floating gate 5 must be increased. However, if the area of the floating gate 5 is increased, then the superposed area of the control gate 6 and floating gate 5 is increased. The capacitance of capacitor C1 is thereby increased. However, the superposed area of the floating gate 5 and channel region 3 is also increased, which increases the capacitance value of capacitor C3. According to formula (1) above, the capacitance coupling ratio CC is therefore not effectively increased.
To increase the coupling ratio CC effectively, only the capacitance of capacitor C1 should be increased. This can be done in the following ways. First, a ferroelectric having a large dielectric constant can be used as the insulating layer 9 between control gate 6 and floating gate 5. Presently, a stack structure of a dielectric layer having an effective dielectric constant greater than that of a silicon layer may be used as the above-mentioned insulating layer 9. A silicon oxide layer/nitride layer/silicon oxide layer or nitride layer/silicon oxide layer may be used as the stack structure of such a dielectric layer. However, such a ferroelectric having a large dielectric constant is not reliable in a high electric field.
Alternatively, the coupling ratio CC can be increased by decreasing the thickness of the insulating layer 9 formed between control gate 6 and floating gate 5. However, if the thickness of insulating layer 9 is too thin, the reliability of the nonvolatile memory cell is sharply reduced in a high electric field. Therefore, making the insulating layer 9 thinner has encountered limitations in the manufacturing technology.
Third, to increase the coupling ratio CC, only the superposed area of floating gate 5 and control gate 6 can be increased while the superposed area of floating gate 5 and channel region 3 is not increased. Such a method is disclosed in U.S. Pat. No. 5,089,869, in which the effective surface area of capacitor C1 is increased using a texturized polysilicon process. However, this method is so complicated and difficult that the reliability of the insulating layer is not assured. This prevents the disclosed method from being easily used.